We are now in a position to take everything that we learned about the theory and practice of memory devices. And actually, set out to build chips that implement all this functionality. So project three begins with all the chips that you designed in projects one and two as well as a primitive data flip flop that you can use as you see fit. And based on these building blocks, we have to build the following chips. We've seen all these chips in one way or another in the previous units. And now we actually implement them. Now most of these chips, all of them, except for the program counter constitute a family of increasingly complicated sequential chips, beginning from one bit register all the way to a randomized that contains more or less 16,000 registers, 16K registers. So let us begin with the one bit register with diagram and documentation is, is repeated here. We've discussed it before. Here is the subfile. There's nothing special about it and the implementation is something that Noam described in, in previous units. So, it can just follow up what is w ritten here, and build this this chip in SDL. Moving along, we can take a set of such single bit registers and build from it a 16-bit register. The HDL is shown here and all we have to do is create the right wiring and what you have is a 16-bit register. So now we are ready to move on and build our first RAM device consisting of eight registers. Here is the API of this chip. Here is the, the stub file that describes its input and output pins. So now that we have all this information, lets figure out how, how we can actually build such a, such a RAM device. So, I can give you two very important tips. The first one is that you have to take the in value and fit it simultaneously to all eight registers so called at the same time. So you use HDL statements to fan out this this incoming value and send to all the registers in the RAM device. And then you use some mux and dmux logic in order to select the exact register that you want to be effected by the respective read or write operation. So, once again, you send information to all the registers, but only one of them is going to be selected using this mux and demux functionality. Now, I want to leave you the details because otherwise you won't be sufficiently challenged I think. And with these details, you have everything that you need in order to, to build this this RAM device. Moving along we have implemented the first three chips and we are ready to to construct the more elaborate RAM64, 512 and so on chips in the hierarchy. So this is our next task and here's how we do it. We start with a RAM chip that we just discussed and we stack together eight such RAM chips. And what comes out is or what results is what we call a RAM64. We can take eight such RAM64s. Put them together to yield the next chip in our hierarchy, which is RAM512. And we can do two more steps of a very similar nature and end up with the most elaborate RAM chip the one that we have called RAM16K. So we basically repeat the same collate recursive ascent, if you will. And and by using this this strategy, we can build more and more elaborate RAM chips. Now how do we do it? Well first of all, we note that a RAM device can be built by grouping together smaller RAM parts, which is, you know, an HDLl description of what I did before in this diagram. And we can think about the address input, which is not shown here, but, you know, it's in the background. We can think about the address input of every one of these chips as a binary value that consists of two logical fields. One field can be used to select the exact RAM, RAM part on which you want to operate and the second field can select the very register within this RAM part that you want to affect by either reading or, or writing something into this register. So taken together u, this these two tricks can enable you to build RAM devices of arbitrary length. And you use mux and demux gates in order to effect this hierarchical addressing scheme that I just described. So, once again, you have here enough tips to to enable you to complete the implementation on your own using HDL. So this basically completes the construction of the RAM devices and we move on to construct the last chip in this project, which is something completely different. It is a, a program counter which is just a fancy name for a counter. In fact, it is not a fancy name. It's, it's it's called program counter, because later on in the overall construction of our computer, it will serve as a program counter. But effectively, it is just a counter. It has an input value. It has an output value and three control bits. Now the overall behavior of this counter is somewhat elaborate. We discussed it when we talked about counters before. I, I want just to emphasize the four most important things about it. This being a counter, we want to be able to set it to zero. We want to be able to set it to some other value like 17 or 19 or whatever. We want to be able to tell the chip to start counting, to change in every cycle into whatever it was before plus 1. And in some cases, we want to tell it perhaps to stop counting and freezes, so to speak. So what you have to do is to come up with with the right functionality, the gate logic that effects everyone one of these four operations. It turns out that you can do it using a register chip, an incremental chip and a bunch of other logic gates that were previously described. So taken together this is what you have to do in in project three. As usual, you go to the Nand2Tetris website and you will find the project webpage with lots of additional operational details. Once again, I want to emphasize for the third time in this course that if you have downloaded the course software suite, there's no need to download anything in addition. This is just for documentation purposes. And you already have all the necessary files on your computer in the directive projects slash zero three and you have your hardware simulator and you're set to go and, and build all these chips on your own. As usual it makes sense to consult these resources when, when necessary. And finally all the best practice advice that was given in previous project is relevant here as well, so you might as well read it before you set out to build a project. And in addition as usual, you will have to use chips that you implemented in previous projects. And as I explained before, the best practice is to ignore your HDL implementations and use the built-in implementations instead. Finally, there's one more point that I'd like to emphasize on this project and that is that the HDL files of this project are stored in two separate directories called a and b. And this structure should remain as is. Now why do we do it? Well, if you recall our RAM devices are built from smaller RAM parts. And, and the smaller RAM parts are built from even smaller RAM parts and it goes on and on. It's like a Russian doll system. And if you take one of these huge RAM chips, let's say RAM16K and put it into the hardware simulator, the simulator begins to evaluate all the chip parts and it does it in, in some sort of a recursive drilling downward. All the way down to single bit registers and it turns out that this can be too much, too much memory or too may objects to handle for, for the hardware simulator, which is just a humble computer program. And therefore, by putting the registers I'm sorry, by putting these RAM chips in two separate directories, we force the simulator to at some point, stop using the HDL files and use and, and start using the the Java implementation of these built-in chips. And this, this will make the implementation or I'm sorry, this will make the simulation much faster and smoother. So please just leave the directory structure as is and you're set to go. So this has been a description of what you have to do in project three and as usual we will now turn to the next unit in which we give you some broader perspective of the notion of memory devices.