So now that you are familiar with HDL and hardware simulation, we are ready to get our hands dirty and actually go and develop some chips. So in this unit we're going to give you all the information that you need in order to design the chips that we have to build in Project 1. Before we go on, let us remind ourself, what is the general spirit of this course? Well, the story that we're telling you is that God told us, here's a logic gate, Nand, now go and build a computer. And when we asked how can we possibly do that, God said one step at a time. And in particular, the hack computer that we are going to build in this course consists of something like 30 different chips. And we are going to build them one step at a time. And in the first project we start with Nand, which is God given, or given by us, or you can think about it as some sort of an axiom that you can assume. And using Nand, we want you to build the following gates. Not, And, Or, Xar, and so on and so forth. So that's what you have to do for Project 1. And why these particular 15 gates? That's a good thing to ask, and the answer is two fold. First of all, every one of these gates is widely used in almost any construction of a digital device or some version of these gates. And the second answer, which is more practical, is that these gates comprise all the elementary logic gates which are needed in order to build our computer. So Project 1 lays out the foundation that we are going to use in subsequent projects, because in other projects, we're going to use these chips, in order to build more complex and more interesting functionality. So, once again, here are the chips that we have to build, and I have separated them into three categories, just that we can discuss it in a more organized fashion. So we have some elementary logic gates, widely familiar: Not, And, Or, and so on. We have 16-bit variants of some of the logic gates. And we have some multi-way, and also multi-way 16-bit variants of the previous gates. And in order to make all these new concepts more familiar, I will focus on some gates in every one of these categories and say few words about them. And this, once again, will give you everything that you need In order to build any one of the gates in Project 1. So without further ado, let's start to talk about multiplexors and demultiplexors. So what is a multiplexor? A multiplexor is a gate that operates as follows. There are two inputs coming in, and we know them a and b. And there's a sel input coming in, so-called, from the bottom. Of course in reality there's no bottom and left, but I'm talking about this gate diagram here. So three inputs come in, a, b, and sel. What does the multiplexor do? Well, if sel = 0, the multiplexor outputs a. If sel = 1 the multiplexor outputs b. That's it, that's the desired behavior of a multiplexor. And here is the truth table of the mulitplexor. We have three inputs, so we have eight different possibilities. And you can convince yourself that the truth table is consistent with what we described before. We can also provide an abbreviated truth table of the multiplexor operation, and once again if sel is 0, the multiplexor outputs a, otherwise it outputs b. So a 2-way multiplexor enables us to select and output one out of two incoming inputs. And this is a fundamental operation that is being used over and over again, both in digital design projects as well as in communications networks. So here's an example of how Mux logic comes to play in the context of building what is sometimes called a programmable gate. Now what is a programmable gate? It's a gate that can behave in one of several different ways according to our will. So here's a simple programmable gate that can act either as an And gate or as an Or gate. If the select bit is zero, the gate acts as And. If the select gate is one, the gate acts as Or. And here is the truth table of the gate, and you can convince yourself that it's consistent with what I said earlier. And here is how I can actually build it. I can use two gates, an And and an Or, provided of course that I have developed them previously. And I can feed the a and b inputs simultaneously to both And and Or. And we called this, before, fanning out. So the a input is fanned out into both And and Or, and the same treatment is done with the b signal. And then I use a single multiplexor to decide if I want to output the result of the And or the result of the Or. So the user of this gate that sees only the interface of the gate, gets exactly what he or she wanted, a programmable gate. Here is the HDL code that implements this particular architecture, and if you want, you can stop the video and inspect this code, and make sure that it's consistent with the gate diagram. So here's an example of a Mux in the context of a digital design application. How do we build a multiplexor? Well we get all this information from the system architect and we also get a stub file, and what we have to do, of course, is to write the HDL code. And it turns out that we can build a multiplexor using three gates, And, Or and Not, which we wire in a certain clever way, and the result is the desired Mux logic. So it's up to you to figure out how to do the wiring and actually implement the desired multiplexor. All right, moving along, let us talk about demultiplexor. A demultiplexor looks like the inverse of a multiplexor. It receives a single input, and based on the selection bit, it either channels the input to an a output, or to a b output. Okay, so it's kind of a distributor of a value into one of several possible channels. In this example we have, it's a two way multiplexor, so it's a relatively simple example. All the other channels get 0. Okay, and so the DMux is basically an inverse of a Mux, DMux is an inverse of a Mux. If you don't like my pronunciation, and once again it distributes a single input into one of several possible output channels. Once again, just like we said about the multiplexor, demultiplexing is also something which is widely used in digital design projects, as well as in communication networks. And we're going to get, or you're going to get the stub file, and you actually have to implement the logic in HDL. All right, I'd like to give you an example of how multiplexing and demultiplexing can come to play in the context of communications networks. So here's a typical situation in building a network. And the situation is such that we may have several channels coming in. Let's say channels of music or several movies that we want to send over a single communications line. So the single line that goes here in the middle of the slide can be 5,000 kilometers long. And it may be sort of an under water line, and or satellite line, and through this single line, I want to send multiple messages. How can I possibly do it. Well if everything is digital, I can put a Mux in the sending end of our story. And I can feed the Mux and ongoing train of 0101010. This can be done using what is known as an oscillator. And because the Mux is going to get a repetitive frame of 0101, it is going to output blue, red, blue, red, blue, red. In every cycle the Mux will output one bit from one of the two inputs. At the receiving end of this story I once again I put a different oscillator and therefore the dmux is going to distribute the incoming inputs according to the DMux logic. It will output blue, red, blue, red, blue, red, blue, red and so on. So this logic here, the DMux and the Mux logic taken together enable me to braid or interleave several messages over a single communications line, which may be very expensive and therefore, it pays off to use it for multiple messages. And by the way, another attractive thing about this scheme here is that it can be completely asynchronous, right? They don't have to operate according to a master clock. Every one of these two operations, the encoding and the decoding operations can be done separately. All right, so we talked about Mux and DMux which were, by far, the most complicated shapes in the elementary logic gates that you have to build. And let's go on and talk about one example of out of the four 16-bit chips that you have to build. So we'll talk about And16, and And16 looks as follows. We have two inputs coming in, both of them are 16-bit buses, and we have a single 16-bit bus coming out. And basically what we have to implement is a 16-bit And operation. So, it looks like this. One and zero should give us one, I'm sorry, zero, zero and zero is zero. One and one finally gives us one. And so on and so forth. We're going to get one if and only if both inputs are one in the respective index that we are looking at. Now, there's something which is a little bit deceiving in this example here because the calculation of the logic here is not sequential, everything is being outputed, boom, in pollen. And this also gives you some tip on how to actually build it, okay. This is a straightforward extension of Elementary endgates, you can read more if you want about how to handle buses of data in HTML. And basically once you get this sub file we can implement an endgate using a set of two way endgates. All right, so this has been what I wanted to say about the 16-bit variants that you have implement. And finally I want to discuss one example of the multi-way variants which happens to be actually quite a straight forward notion. Here's an example of Mux 4-way 16. It has four inputs coming in, everyone of them is a 16-bit bus. We have 2-bit selection coming in and that is because you need 2-bits in order to select four different possibilities. And we have the stub file and we can build this thing using several Mux 16 gates as well as perhaps some other gates as needed. So what do we have to do in project one? Once again, we have to implement all these gates starting with nothing more Then NAND and previously designed gates. So once you build Not, you're welcome to use it. Once you go Not and And, you're welcome to use any one of these two gates and so on and so forth. So how do we actually do it? How do we actually build every one of these gates? Well, we're going to give you some building materials and we're going to use soar as an example. So we have, you have the gray diagrams from the book or from the lecture we're going to give you this HDL file which is available to you and you can open it up In a text editor. And we also going to give you a text script and a compare file. And here is the contract that we want you to play with, or to play by the rules of this contract. When you run your Xor HDL. That is, once you take this Xor file and implement it and add your own HDL. When you run the resulting Xor HDL file on the supplied Xor test, the test we provide, your output file should be the same as the supplied compare file. If this will happen you have built a chip to our satisfaction. Once again if your chip generates the expected behavior that we have specified then you were done with this chip and you can go on to develop the next one. So for every chip that you have to develop, we're going to give you stub file, test script, and a compare file. All right, so the resources of Project 1 are listed in the nand2tetris website. You can look at the different files if you want and there's no need to download anything. Because if you've downloaded the course software suite, then all the necessary files that you need for this project are available in your projects/01 directory. And you're welcome to start working with these files and build Project 1, if you need some additional resources, you can look at what we did in the first week just to sort of get you warmed up for this project. There is the HDL Survival Guide, tutorial, and the Q & A forum, you can consult with any of these resources in order to gain some confidence and actually go out and build Project 1. In closing, I would like to say a few words about what we call the hack chipset API. When you build a particular gate diagram like this one, you're going to use all sorts of chip parts. In this case, two end gates a single or gate and a two converters or two not gates. And the question is how are you supposed to know what are the names of the input and output files, I'm sorry the input and output pins of every one of the gates that you want to use? Well, the answer is that if the gates that you use are so-called off the shelf gates, or if they are part of the hack chipset API, we provide all the necessary information about how to use them. And in particular, there is a document on the nand2tetris website that gives you the API of all the chips in the Hack chipset. This document is actually part of the HDL Survival Guide, so whenever you're not sure, what are the names of the inputs and outputs pins of a particular chip part. Please consult this document and you will know how to use them, another thing that I'd like to say in closing before we end this unit is that you can always use what we call built-in chips. For example suppose you implement some chip called Foo and you want to use a chip part called Bar. How can you do it if you haven't written Bar before? It sounds a little bit impossible but in fact, it is possible, so once again, if you don't implement some chips that are part of the chip of the Hack chipset, you can still use them as chip-parts. All you have to do, if we gave you the stub file of Bar, you have to change the name of this file to something else. For example, instead of calling it Chipname.hdl, you can rename it chipname.hdl1. Once you do this, when you load Foo into the hardware simulator, the simulator will look for and hdl file that corresponds to the missing chip part, and if it will not find it It will by default revert to using the built in implementation of the missing chip. So this gives us tremendous flexibility because it means that in principle we can build these chips in any order that we please although we recommend that you build the chips in the given order that they are listed in Project 1. So here are some general best practice advice for Project 1 and subsequent projects as well. Once again, we recommend that you build the chips in the given order because they are specified from the simpler to the more complex. If you don't implement something you can put it aside and if you want get back to it later, and you can if you want design some helper cheats. You know cheats that we haven't specified which will act like private methods in high level programming. However this is really not necessary, and we advise that you don't do it, there's no need to invent any new chips, just use the chips that we provided and you should be fine in completing this project. And in general and just like we always do in computer science, strive to use as few parts as possible, try to create an implementation which is elegant, readable, and well done. Now, I'd like to end this unit with a few notes about frequently asked problems and questions that students raised when working on Project 1. First of all, you have to realize that when you create your HDL program, you have to use some external text editor like notepad or whatever editor of your liking. You cannot create HDL code using our tools, in particular, you cannot write code inside the simulator. Once again do it in an external editor and once you save your HDL file you can load it into our simulator. The next point that confused some students is that you cannot use a chip as a chip part in its own implementation, there's no recursion in HDL. All right, so all the chips to use when implementing a new chip has to be some other chips that you've implemented before, or some built in chips, which are always available as well. Now, when you run your HDL in a simulator if everything works well you will get a message at the bottom left of the simulation saying something like simulation completed successfully. If something goes wrong and if there's a syntax problem with their HDL code or anything like that, you will get an error message printed in red. So once again, some students tended to miss these messages so pay attention to the bottom left of the simulator when you simulate your chips. Now, in unit 1.6, Norm explained the whole notion of multi-bit busses, and one thing I would like to add to this discussion is that, these busses are indexed from right to left. So if A is a 16 bit bus, then A[0] stands for the right-most bit, sometimes called the least significant bit or the LSB. And A[15] stands for the left-most bit, also called the most significant bit or the MSB. So, this is just a convention that you have to keep in mind when you index your multi-bit busses, and finally we want to emphasize once again that we provide all sorts of resources with which you can consult. When you write HDL code, in particular, the book has whole appendix dedicated to HDL programming and this appendix is also available online in the nand2tetris website. And there is an excellent document called HDL Survival Guide, which was written by Mark Armbrust, and this is the first place that you have to go to when you get stuck with something and you need some advice. So this has been the end of our unit about Project 1 overview and we are ready to go onto the last unit of this week, in which we are going to talk about some general observations, about elementary logic gates. [BLANK AUDIO]
